The present invention relates to circuits which include multi-layer thin film elements exhibiting giant magnetoresistance (GMR), and more specifically to techniques for resistively trimming such circuits with high degrees of accuracy and precision. Even more specifically, the present invention provides techniques by which (1) the value of a GMR resistor can be adjusted, (2) the output of a transpinnor logic gate can be adjusted, and (3) the gain of each channel of a transpinnor differential amplifier can be adjusted so that its output will be zero even though its two input lines may have different resistances.
Resistive trimming is a technique used to fabricate resistors to a specified accuracy. A standard trimming technique known as laser trimming uses a laser to burn out individual portions of a bank of resistors with binary-sequenced values. This technique is unsatisfactory for many applications in that it is expensive, labor intensive, time consuming, irreversible, and limited in its minimum adjustment to the smallest discrete resistor value in the resistor bank. Moreover, the size of the resistor bank must be such that the spacing between resistors is larger than the spot size of the laser, typically on the order of a micron. This results in an unacceptably large amount of die space for most applications. This is exacerbated by the fact that the typical resistor bank is many time larger than the minimum feature size of many of the devices in which trimmed resistors have potential applications.
One potential application for resistive trimming is in balancing the many sense/reference line pairs in a memory device such as, for example, a memory device based on GMR structures, an example of which is described in U.S. Pat. No. 5,587,943 for NONVOLATILE MAGNETORESISTIVE MEMORY WITH FULLY CLOSED FLUX OPERATION issued on Dec. 24, 1996, the entire disclosure of which is incorporated herein by reference for all purposes. That is, random variations that may occur during fabrication of such devices result in line pairs that are not matched closely enough. Such resistance mismatches depend on a number of different factors including, for example, feature size, process stability, and point-to-point variations in film properties such as thickness, crystallite structure, stoichiometry, and layering effect variations.
Unfortunately, laser trimming would be unsuitable for such memory devices in that line widths and line spacing of less than 0.5 microns (even down to 100 nm) are anticipated. The size of the resistive banks necessary for laser trimming would not only be prohibitively expensive, but would account for most of the die area, subverting any gains in miniaturization.
In view of the foregoing, it is desirable to develop resistive trimming techniques for nanoscale devices in which the resistive trimming overhead comprises only a small portion of the overall device size. It is further desirable that such techniques allow greater trimming precision, can be automated under computer control, and are reversible so that resistance values can be adjusted to compensate for changing conditions.
According to the present invention, resistive trimming techniques are provided which address all of the shortcoming described above. That is, the present invention provides a technique referred to herein as magnetoresistive trimming which manipulates resistance values through the application of magnetic fields to giant magnetoresistive (GMR) structures.
Thus, the present invention provides an electronic device including at least one configurable resistive element having a resistance value associated therewith. Each such configurable resistive element includes at least one multi-layer thin film element exhibiting giant magnetoresistance. The resistance value of each configurable resistive element is configurable over a resistance value range by application of at least one magnetic field which manipulates at least one magnetization vector associated with the thin film element. According to various embodiments, the configurable resistive elements comprise a single multi-layer thin film element. According to other embodiments, the configurable resistive elements comprise active GMR devices described herein as xe2x80x9ctranspinnorsxe2x80x9d which exhibit characteristics of both transistors and transformers.
According to another specific embodiment, a method for matching first and second resistance values in a memory is provided. The first and second resistance values are associated with first and second memory access lines, respectively. A configurable resistive element comprising at least one multi-layer thin film element exhibiting giant magnetoresistance is associated with at least one of the first and second memory access lines. The magnetization of the thin film element is manipulated such that the first and second resistance values match within a specified tolerance.
According to yet another embodiment of the invention, a method for accessing a memory having first and second pluralities of access lines is provided. The second plurality of access lines comprises pairs of access lines, each of which have a resistive element associated therewith comprising at least one multi-layer thin film element exhibiting giant magnet resistance. The magnetization of the thin film element is configured such that each pair of access lines carries equal currents when the memory bits on the two lines are in identical magnetic states. According to this embodiment, individual memory cells in the memory are accessed using coincident currents in corresponding ones of the first and second pluralities of access lines.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.